 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 for more information www.linear.com/LTM4650-1 typical a pplica t ion descrip t ion dual 25a or single 50a module regulator with 0.8% dc and 3% transient accuracy the lt m ? 4650-1a/LTM4650-1b is dual 25a or single 50a output step-down module ? ( power module) regulator with 0.8% (LTM4650-1a) and 1.5% (LTM4650-1b) total dc output error with 3% transient output error. included in the package are the switching controller , power fets , inductors, and all supporting components. external compensation allows for fast transient response to minimize output capacitance when powering fpgas, asics, and processors. with synchronized multiphase parallel current sharing , six LTM4650-1 devices can de - liver up to 300a. the LTM4650-1 is offered in a 16mm 16mm 5.01 bga package, with snpb (bga) or rohs compliant terminal finish. fea t ures a pplica t ions n 0.8% maximum total dc output error over line and load (LTM4650-1a) n 3% transient output error with minimum output?capacitance n dual 25a or single 50a output n 4.5v to 15v input, 0.6v to 1.8v output voltage range n differential remote sense amplifer n current mode control/fast transient response n current sharing up to 300a n 16mm 16mm 5.01mm bga package n fpga, asic, processor core voltage regulation n information, communication systems l, lt , lt c , lt m , linear technology, the linear logo, module, burst mode, ltpowercad and polyphase are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. other patents pending. 50a, 1.0v output dc/dc module regulator 1.0v output efficiency, f sw = 500khz 25% load step transient response, 3% output regulation window. 12v in , 1.0v out , 50a with 6x 220f ceramic cap * 46501 ta01a LTM4650-1 v in 220f ceramic 4v 6 68pf v out1 v fb1 v fb2 v outs2 comp2 v out2 1.0v 50a mode_pllin sgnd phasmd gnd comp1 v out2 diffp diffn diffout 90.9k 121k v in 4.5v to 15v 120k 0.1f 22f 25v 4 4.7f temp run1 run2 track1 track2 intv cc pgood1 pgood2 f set pins not used in this circuit: clkout extv cc sw1 sw2 v outs1 10k 10nf 3.24k v in = 5v v in = 12v v out 20mv/div ac-coupled load step 10a/div 50s/div 46501 ta01c 54mv 12.5a step *see demo circuit dc2479a-b ltm 4650-1 46501fc 70 75 80 85 90 95 efficiency (%) 46501 ta01b load current (a) 0 10 20 30 40 50 65
2 for more information www.linear.com/LTM4650-1 p in c on f igura t ion a bsolu t e maxi m u m r a t ings (note 1) o r d er i n f or m a t ion v in .............................................................. C 0.3 v to 16 v v sw 1 , v sw 2 .................................................... C1 v to 16 v pgood 1, pgood2, run 1, run 2, intv cc , extv cc .......................................... C 0.3 v to 6v mode _ pllin , f set , track 1, track 2, diffout , phasmd ............................... C 0. 3 v to intv cc v out 1 , v out 2 , v outs 1 , v outs 2 ( note 6) ........ C 0. 3 v to 6v diffp , diffn ......................................... C 0.3 v to intv cc intv cc peak output current ................................ 10 0 ma internal operating temperature range ( no te 2) ............................................. C 4 0 c to 125 c storage temperature range .................. C 5 5 c to 125 c peak package body temperature .......................... 24 5 c bga package 144-lead (16mm 16mm 5.01mm) top view temp clkout sw1 phasmd extv cc 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a sw2 pgood1 pgood2 run2 track2 intv cc v outs2 diffp diffout diffn run1 track1 mode_pllin v fb1 v outs1 f set sgnd comp1 comp2 sgnd v fb2 v in v out2 gnd gnd v out1 sgnd gnd t jmax = 125c, e ja = 7c/w, e jcbottom = 1.5c/w, e jctop = 3.7c/w, e jb + e jba 7c/w e values defined per jesd 51-12 weight = 3.5g part number pad or ball finish part marking* package type msl rating total dc accuracy temperature? range (note 2) device finish code LTM4650 ey- 1a#pbf sac305 (rohs) LTM4650 y- 1 e1 bga 3 0.8% C40c to 125c LTM4650 iy- 1a#pbf sac305 (rohs) LTM4650 y- 1 e1 bga 3 0.8% C40c to 125c LTM4650 ey- 1b#pbf sac305 (rohs) LTM4650 y- 1 e1 bga 3 1.5% C40c to 125c LTM4650 iy- 1b#pbf sac305 (rohs) LTM4650 y- 1 e1 bga 3 1.5% C40c to 125c LTM4650 iy- 1a snpb (63/37) LTM4650y- 1 e0 bga 3 0.8% C40c to 125c LTM4650 iy- 1b snpb (63/37) LTM4650y- 1 e0 bga 3 1.5% C40c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? recommended bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? bga package and t ray drawings: www.linear.com/packaging http://www .linear.com/product/LTM4650-1#orderinfo ltm 4650-1 46501fc 3 for more information www.linear.com/LTM4650-1 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range. specified as each individual output channel. t a = 25c (note 2), v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 24. symbol parameter conditions min typ max units v in input dc voltage l 4.5 15 v v out output dc voltage l 0.6 1.8 v v out1(dc) , v out2(dc) output voltage, total variation with line and load c in = 22f 3, c out = 100f 2 ceramic, 470f poscap v in = 12v, v out = 1.2v, i out = 0a to 25a a-grade (0.8%) b-grade (1.5%) l l 1.190 1.182 1.210 1.218 v v input specifications v run1 , v run2 run pin on/off threshold run rising 1.1 1.25 1.40 v v run1hys , v run2hys run pin on hysteresis 150 mv i inrush(vin) input inrush current at start-up i out = 0a, c in = 22f 3, c ss = 0.01f, c out = 100f 3, v out = 1.2v 1 a i q(vin) input supply bias current (both channel running v in = 12v, v out = 1.2v, burst mode operation v in = 12v, v out = 1.2v, pulse-skipping mode v in = 12v, v out = 1.2v, switching continuous shutdown, run = 0, v in = 12v 4.5 25 240 35 ma ma ma a i s(vin) input supply current v in = 4.5v, v out = 1.2v, i out = 25a v in = 12v, v out = 1.2v, i out = 25a 8.4 3.2 a a output specifications i out1(dc) , i out2(dc) output continuous current range v in = 12v, v out = 1.2v (note 6) 0 25 a v out1(line) /v out1 v out2(line) /v out2 line regulation accuracy v out = 1.2v, v in from 4.5v to 15v i out = 0a for each output, l 0.01 0.1 %/v v out1 /v out1 v out2 /v out2 load regulation accuracy for each output, v out = 1.2v, 0a to 25a v in = 12v (note 6) a-grade b-grade l l 0.1 0.2 0.4 0.75 % % v out1(ac) , v out2(ac) output ripple voltage for each output, i out = 0a, c out = 100f 3 ceramic, 470f poscap, v in = 12v, v out = 1.2v, frequency = 500khz 15 mv p-p f s (each channel) output ripple voltage frequency v in = 12v, v out = 1.2v, f set = 1.25v (note 4) 500 khz f sync (each channel) sync capture range 400 780 khz v outstart (each channel) turn-on overshoot c out = 100f ceramic, 470f poscap, v out ?= 1.2v, i out = 0a v in = 12v 10 mv t start (each channel) t urn-on t ime c out = 100f ceramic, 470f poscap, no load, track/ss with 0.01f to gnd, v in = 12v 5 ms v out(ls) (each channel) peak deviation for dynamic load load : 0% to 50% to 0% of full load c out = 22f 3 ceramic, 470f poscap v in ?=?12v, v out = 1.2v 30 mv ltm 4650-1 46501fc 4 for more information www.linear.com/LTM4650-1 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range. specified as each individual output channel. t a = 25c (note 2), v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 24. symbol parameter conditions min typ max units t settle (each channel) settling t ime for dynamic load step load: 0% to 50% to 0% of full load, v in = 12v, c out = 100f, 470f poscap 20 s i out(pk) (each channel) output current limit v in = 12v, v out = 1.2v 35 a control section v fb1 , v fb2 voltage at v fb pins i out = 0a, v out = 1.2v a-grade b-grade l l 0.596 0.594 0.600 0.600 0.604 0.606 v v i fb (note 5) C5 C20 na v ovl feedback overvoltage lockout l 0.64 0.66 0.68 v track1 (i), track2 (i) t rack pin soft-start pull-up current track1 (i),track2 (i) start at 0v 1 1.3 1.5 a uvlo undervoltage lockout (falling) 3.3 v uvlo hysteresis 0.6 v t on(min) minimum on-time (note 5) 90 ns r fbhi1 , r fbhi2 resistor between v outs1 , v outs2 and v fb1 , v fb2 pins for each output 60.05 60.4 60.75 k? v pgood1 , v pgood2 low pgood v oltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 5 a v pgood pgood trip level v fb with respect to set output voltage v fb ramping negative v fb ramping positive C10 10 % % intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 15v 4.8 5 5.2 v v intvcc load regulation int v cc load regulation i cc = 0ma to 50ma 0.75 2 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.7 v v extvcc(drop) extv cc dropout i cc = 20ma, v extvcc = 5v 50 100 mv v extvcc(hyst) extv cc hysteresis 220 mv oscillator and phase-locked loop frequency nominal nominal frequency f set = 1.2v 450 500 550 khz frequency low lowest frequency f set = 0.93v 400 khz frequency high highest frequency f set > 2.4v, up to intv cc 780 khz f set frequency set current 9 10 11 a r mode_pllin mode_pllin input resistance 250 k clkout phase (relative to v out1 ) phasmd = gnd phasmd = float phasmd = intv cc 60 90 120 deg deg deg clk high clk low clock high output v oltage clock low output v oltage 2 0.2 v v ltm 4650-1 46501fc 5 for more information www.linear.com/LTM4650-1 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTM4650-1 is tested under pulsed load conditions such that t j t a . the LTM4650-1e is guaranteed to meet specifications from 0c to 125c internal temperature. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTM4650-1i is guaranteed over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: two outputs are tested separately and the same testing condition is applied to each output. note 4: LTM4650-1 device is designed to operate from 400khz to 750khz. note 5: these parameters are tested at wafer sort. note 6: see output current derating curves for different v in , v out and t a . symbol parameter conditions min typ max units differential amplifier a v differential amplifier gain 1 v/v r in input resistance measured at diffp input 80 k? v os input offset voltage v diffp = v diffout = 1.2v, i diffout = 100a 3 mv psrr differential amplifier power supply rejection ratio 5v < v in < 15v 90 db i cl maximum output current 3 ma v out(max) maximum output voltage i diffout = 300a intv cc C 1.4 v gbw gain bandwidth product 3 mhz v temp diode connected pnp i = 100a 0.6 v tc temperature coefficient l C2.2 mv/c the l denotes the specifications which apply over the specified internal operating temperature range. specified as each individual output channel. t a = 25c (note 2), v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 24. typical p er f or m ance c harac t eris t ics efficiency vs output current, v in = 5v efficiency vs output current, v in = 12v dual phase single output efficiency vs output current, v in = 12v, f s = 500khz 1.5v out , 600khz 1.8v out , 600khz 1.2v out , 500khz 1.0v out , 500khz 0.8v out , 400khz 1.5v out , 600khz 1.8v out , 600khz 1.2v out , 500khz 1.0v out , 500khz 0.8v out , 400khz load current (a) 0 65 efficiency (%) 90 85 80 75 70 95 20 30 40 50 10 46501 g03 1.5v out , 600khz 1.8v out , 600khz 1.2v out , 500khz 1.0v out , 500khz 0.8v out , 400khz ltm 4650-1 46501fc 70 75 80 85 90 95 efficiency (%) 46501 g01 load current (a) 0 load current (a) 5 10 15 20 25 65 70 75 80 85 0 90 95 efficiency (%) 46501 g02 5 10 15 20 25 65 6 for more information www.linear.com/LTM4650-1 typical p er f or m ance c harac t eris t ics single phase short circuit protection with 25a single phase start-up with 25a single phase short circuit protection with no load 1.5v dual phase single output load transient response 1.8v dual phase single output load transient response single phase start-up with no load 20ms/div v sw 10v/div v out 0.5v/div i in 0.2a/div 46501 g09 12v in , 1.2v out , 500khz c out = 1 470f poscap + 2 100f ceramic, c ss = 0.1f 50 s/div v sw 10v/div v out 0.5v/div i in 1a/div 46501 g10 12v in , 1.2v out , 500khz c out = 1 470f poscap + 2 100f ceramic, c ss = 0.1f 20ms/div v sw 10v/div v out 0.5v/div i in 1a/div 46501 g11 12v in , 1.2v out , 500khz c out = 1 470f poscap + 2 100f ceramic, c ss = 0.1 f 50s/div v sw 10v/div v out 0.5v/div i in 2a/div 46501 g12 12v in , 1.2v out , 500khz c out = 1 470f poscap + 2 100f ceramic burst mode and pulse-skip mode efficiency v in =12v, v out = 1.2v, f s = 500khz 1v dual phase single output load transient response 1.2v dual phase single output load transient response load current (a) 0.01 0 10 20 30 efficiency (%) 90 80 70 60 50 40 100 1 10 0.1 46501 g04 pulse-skip mode burst mode operation ccm 50s/div v out(ac) 20mv/div load step 10a/div 46501 g05 12v in , 1v out , 500khz, 12.5a load step, 10a/s step-up and step-down c out = 6 220f ceramic c ff = 68pf 50s/div v out(ac) 20mv/div load step 10a/div 46501 g06 12v in , 1.2v out , 500khz, 12.5a load step, 10a/s step-up and step-down c out = 6 220f ceramic c ff = 68pf 50s/div v out(ac) 20mv/div load step 10a/div 46501 g07 12v in , 1.5v out , 600khz, 12.5a load step, 10a/s step-up and step-down c out = 6 220f ceramic c ff = 68pf 50s/div v out(ac) 20mv/div load step 10a/div 46501 g08 12v in , 1.8v out , 600khz, 12.5a load step, 10a/s step-up and step-down c out = 6 220f ceramic c ff = 68pf ltm 4650-1 46501fc 7 for more information www.linear.com/LTM4650-1 p in func t ions v out1 (a1-a5, b1-b5, c1-c4): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. review table 4. gnd (a6-a7, b6-b7, d1-d4, d9-d12, e1-e4, e10-e12, f1-f3, f10-f12, g1, g3, g10, g12, h1-h7, h9-h12, j1, j5, j8, j12, k1, k5-k8, k12, l1, l12, m 1 , m12): power ground pins for both input and output returns. v out2 (a8-a12, b8-b12, c9-c12): power output pins. apply output load between these pins and gnd pins. rec - ommend placing output decoupling capacitance directly between these pins and gnd pins . review t able 4. v outs1 , v outs2 (c5, c8): this pin is connected to the top of the internal top feedback resistor for each output. the pin can be directly connected to its specific output, or connected to diffout when the remote sense amplifier is used. in paralleling modules, one of the v outs pins is connected to the diffout pin in remote sensing or directly to v out with no remote sensing. it is very important to connect these pins to either the diffout or v out since this is the feedback path, and cannot be left open. see the applications information section. f set (c6): frequency set pin. a 10 a current is sourced from this pin . a resistor from this pin to ground sets a voltage that in turn programs the operating frequency. alternatively, this pin can be driven with a dc voltage that can set the operating frequency. see the applications information section. sgnd (c7, d6, g6-g7, f6-f7): signal ground pin. return ground path for all analog and low power circuitry . tie a single connection to the output capacitor gnd in the ap - plication. see layout guidelines in figure 13. v fb1 , v fb2 (d5, d7): the negative input of the error amplifier for each channel. internally, this pin is con - nected to v outs1 or v outs2 with a 60.4k? precision resistor. different output voltages can be programmed with an additional resistor between v fb and gnd pins. in polyphase ? operation, tying the v fb pins together allows for parallel operation. see the applications information section for details. track1, track 2 (e5, d8): output voltage tracking pin and soft-start inputs . each channel has a 1.3a pull-up current source . when one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. the remaining channel can be set up as the slave, and have the masters output applied through a voltage divider to the slave out - puts track pin. this voltage divider is equal to the slave output s feedback divider for coincidental tracking . see the applications information section. comp1, comp 2 (e6, e7): current control threshold and error amplifier compensation point for each channel. the current comparator threshold increases with this control voltage. comp pin internal has 10 pf filter cap to sgnd. an external rc filter circuit is required for control loop compensation. see applications information section. tie the comp pins together for parallel operation. do not drive this pin. diffp (e8): positive input of the remote sense amplifier . this pin is connected to the remote sense point of the output voltage. see the applications information section. diffn (e9): negative input of the remote sense amplifier. this pin is connected to the remote sense point of the output gnd. see the applications information section. (recommended to use test points to monitor signal pin connections.) package row and column labeling may vary among module products. review each package layout carefully. ltm 4650-1 46501fc 8 for more information www.linear.com/LTM4650-1 p in func t ions mode_pllin (f4): force continuous mode , burst mode operation, or pulse-skipping mode selection pin and external synchronization input to phase detector pin. connect this pin to sgnd to force both channels into force continuous mode of operation . connect to intv cc to enable pulse-skipping mode of operation. leaving the pin floating will enable burst mode operation. a clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. run1, run 2 (f5, f9): run control pin. a voltage above 1.25v will turn on each channel in the module. a voltage below 1.25 v on the run pin will turn off the related chan - nel. each run pin has a 1a pull-up current, once the run pin reaches 1.2 v an additional 4.5a pull-up current is added to this pin. diffout (f8): internal remote sense amplifier output. connect this pin to v outs1 or v outs2 depending on which output is using remote sense . in parallel operation con - nect one of the v outs pin to diffout for remote sensing. sw1, sw 2 (g2, g11): switching node of each channel that is used for testing purposes. also an r-c snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. see the applications information section. phasmd (g4): connect this pin to sgnd, intv cc , or float- ing this pin to select the phase of clkout to 60 degrees, 120 degrees, and 90 degrees respectively. clkout (g5): clock output with phase control using the phasmd pin to enable multiphase operation between devices. see the applications information section. pgood1, pgood 2 (g 9, g 8): output voltage power good indicator. open drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point. intv cc (h8): internal 5v regulator output. the control circuits and internal gate drivers are powered from this voltage. decouple this pin to pgnd with a 4.7 f low esr tantalum or ceramic. intv cc is activated when either run1 or run2 is activated. temp (j6): temperature monitor . an internal diode con - nected npn transistor between this pin and sgnd with 10nf filtering capacitor . see the applications information section. extv cc (j7): external power input that is enabled through a switch to intv cc whenever extv cc is greater than 4.7v. do not exceed 6v on this input, and connect this pin to v in when operating v in on 5v. an efficiency increase will occur that is a function of the (v in C intv cc ) multiplied by power mosfet driver current. typical current requirement is 30ma. v in must be applied before extv cc , and extv cc must be removed before v in . v in (m2-m11, l2-l11, j2-j4, j9-j11, k2-k4, k9-k11): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. (recommended to use test points to monitor signal pin connections.) ltm 4650-1 46501fc 9 for more information www.linear.com/LTM4650-1 s i m pli f ie d b lock diagra m decoupling r equire m en t s symbol parameter conditions min typ max units c in1, c in2 external input capacitor requirement (v in1 = 4.5v to 15v, v out1 = 1.5v) (v in2 = 4.5v to 15v, v out2 = 1.0v) i out1 = 25a i out2 = 25a 44 44 66 66 f f c out1 c out2 external output capacitor requirement (v in1 = 4.5v to 15v, v out1 = 1.5v) (v in2 = 4.5v to 15v, v out2 = 1.0v) i out1 = 25a i out2 = 25a 600 600 800 800 f f t a = 25c. use figure 1 configuration. figure 1. simplified LTM4650-1 block diagram 46501 f01 temp clkout run1 mode_pllin phasemd track1 = 100a or temp monitors 4.7f 0.22f ss cap 1 f c in1 22f 25v 2 v in v in r fb2 60.4k mtop1 mbot1 power control 0.22f 0.12h 60.4k c out1 r fb1 40.2k + v out1 1.5v 25a v out2 1.2v 25a v fb1 gnd gnd v in 4.5v to 15v gnd gnd sw2 sw1 pgood2 pgood1 internal filter 1 f c in2 22f 25v 2 mtop2 mbot2 0.22f 0.12h c out2 + + ? 60.4k v out1 v out2 v fb2 v outs2 v outs1 r fset r th2 c th2 v in r t v in r t ss cap diffout diffn diffp comp1 sgnd track2 intv cc extv cc run2 comp2 f set sgnd 10pf r th1 c th1 10pf ltm 4650-1 46501fc 10 for more information www.linear.com/LTM4650-1 o pera t ion power module description the LTM4650-1 is a dual-output standalone nonisolated switching mode dc/ dc power supply with 0.8% ( a-grade) total dc output error over line, load and temperature varia - tion. it can provide two 25a outputs with few external input and output capacitors and setup components . this module provides precisely regulated output voltages programmable via external resistors from 0.6v dc to 1.8v dc over 4.5 v to 15v input voltages. the typical application schematic is shown in figure 24. the LTM4650-1 has dual integrated constant-frequency current mode regulators and built-in power mosfet devices with fast switching speed. the typical switching frequency is from 400khz to 600khz depending on output voltage. for switching-noise sensitive applications, it can be externally synchronized from 400khz to 780khz. a resistor can be used to program a free run frequency on the fset pin. see the applications information section. with current mode control , the LTM4650-1 module has sufficient stability margins and good transient perfor - mance with a wide range of output capacitors, even with all ceramic output capacitors . current mode control provides cycle-by-cycle fast current limit and foldback current limit in an over current condition. internal overvoltage and undervoltage comparators pull the open-drain pgood outputs low if the output feedback voltage exits a 10% window around the regulation point. as the output voltage exceeds 10% above regulation, the bottom mosfet will turn on to clamp the output voltage . the top mosfet will be turned off. this overvoltage protect is feedback voltage referred. pulling the run pins below 1.1 v forces the regulators into a shutdown state, by turning off both mosfets . the track pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. see the applications information section. the LTM4650-1 has a built-in 10pf high frequency filter cap from comp to sgnd for each output. an external rc filtering circuit is required to achieve fast type ii control loop compensation. table 4 provides a guide line for input, output capacitances and rc comp values for several oper - ating conditions. the linear technology module power design t ool (ltpowercad ? ) will be provided for transient and stability analysis. the v fb pin is used to program the output voltage with a single external resistor to ground. a differential remote sense amplifier is available for sens - ing the output voltage accurately on one of the outputs at the load point , or in parallel operation sensing the output voltage at the load point. multiphase operation can be easily employed with the mode_ pllin, phasmd, and clkout pins. up to 12? phases can be cascaded to run simultaneously with respect to each other by programming the phasmd pin to different levels. see the applications information section. high efficiency at light loads can be accomplished with selectable burst mode operation or pulse-skipping opera - tion using the mode_pllin pin. these light load features will accommodate batter y operation . efficiency graphs are provided for light load operation in the typical performance characteristics section. see the applications information section for details. a general purpose temperature diode is included inside the module to monitor the temperature of the module. see the applications information section for details. the switch pins are available for functional operation monitoring and a resistor-capacitor snubber circuit can be careful placed on the switch pin to ground to dampen any high frequency ringing on the transition edges. see the applications information section for details. ltm 4650-1 46501fc 11 for more information www.linear.com/LTM4650-1 the typical LTM4650-1 application circuit is shown in figure? 24. external component selection is primarily determined by the maximum load current and output voltage. refer to table 4 for specific external capacitor requirements for particular applications. o utput t ot al dc a ccuracy and ac t ransient p erformance in modern asic and fpga power supply designs, a tight total voltage regulation window , 3% for example, is re - quired of the supply powering the core and periphery . to meet this requirement , the supplys dc voltage variance plus any ac voltage variation which may occur during any load step transient must fall within this allowed window. the dc voltage variance is determined by the accuracies of the supplys reference voltage, resistor divider, load regulation and line regulation over the operating tempera - ture range. the ac voltage variance is determined by the supply s output voltage overshoot and undershoots in response to a load transient condition for a given output capacitor network. figure 2 shows a typical load step transient response waveform together with dc voltage accuracy variance. for a given allowable voltage regulation window, a tighter dc voltage accuracy allows more margin for the ac variation due to a load transient response. this increased margin for ac variation allows for a reduction in the total output capacitance required to meet the regulation window re - quirement. this allows for a reduced total solution cost and footprint area . a pplica t ions i n f or m a t ion for example, in an fpga core voltage application, for a 12v input, 0.9 v output at 72a design, a total overall 3% total voltage regulation window is required in responding to a 25% load step transient. figure 3 illustrates the benefit of overall output capacitor reduction versus improved total dc accuracy by using 100f ceramic output capacitors. figure 2. typical load step transient response with dc voltage accuracy variance allowable regulation window dc accuracy load step ac overshoot ac undershoot 46501 f02 total dc accuracy (%) required output capacitance (f) 5000 4000 3000 2000 1000 4500 3500 2500 1500 500 0 0.8 1.5 46501 f03 2.0 1.2 2200 3200 2600 4700 figure 3. overall output capacitor vs total dc accuracy v in to v out step-down ratios there are restrictions in the maximum v in and v out step- down ratio that can be achieved for a given input voltage. each output of the LTM4650-1 is capable of 98% duty cycle, but the v in to v out minimum dropout is still shown as a function of its load current and will limit output cur - rent capability related to high duty cycle on the top side switch . minimum on-time t on( min) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that t on(min) < d/f sw , where d is duty cycle and f sw is the switching frequency . t on(min) is specified in the electrical parameters as 90ns. output voltage programming the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4 k? internal feedback resistor connects between the v outs1 to v fb1 and v outs2 to v fb2 . it is very important that these pins be connected to their respective outputs for proper feedback regulation. overvoltage can occur if these v outs1 and v outs2 pins are left floating when used as individual regulators, or at least one of them is used in paralleled regulators. the output voltage will default to 0.6v with no feedback resistor on ltm 4650-1 46501fc 12 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion either v fb1 or v fb2 . adding a resistor r fb from v fb pin to gnd programs the output voltage: v out = 0.6v ? 60.4k + r fb r fb table 1. v fb resistor table vs various output voltages v out 0.6v 0.8v 0.9v 1.0v 1.2v 1.5v 1.8v r fb open 182k 121k 90.9k 60.4k 40.2k 30.2k for parallel operation of multiple channels the same feed - back setting resistor can be used for the parallel design. this is done by connecting the v outs1 to the output as shown in figure 4, thus tying one of the internal 60.4k resistors to the output. all of the v fb pins tie together with one programming resistor as shown in figure 4. equal to 60.4k for a 1.2v output. four phases connected in parallel equates to a worse case feedback current of 4 ? i fb = 80 na maximum. the voltage error is 80na ? 30.2k = 2.4mv. if v outs2 is connected, as shown in figure 2, to v out , and another 60.4k resistor is connected from v fb2 to ground, then the voltage error is reduced to 1.2mv. if the voltage error is acceptable then no additional connections are necessary . the onboard 60.4k resistor is 0.5% accurate and the v fb resistor can be chosen by the user to be as accurate as needed. all comp pins are tied together for current sharing between the phases. the track/ss pins can be tied together and a single soft-start capacitor can be used to soft-start the regulator. the soft-start equation will need to have the soft-start current parameter increased by the number of paralleled channels. see output voltage tracking section. input capacitors the LTM4650-1 module should be connected to a low ac- impedance dc source . for the regulator input two 22f input ceramic capacitors are required for each channel for rms ripple current. a 47f to 100 f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capaci - tance. if low impedance power planes are used, then this bulk capacitor is not needed . for a buck converter , the switching duty-cycle can be estimated as: d = v out v in without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1 ? d ( ) in the above equation, % is the estimated efficiency of the power module. the bulk capacitor can be a switcher- rated electrolytic aluminum capacitor , polymer capacitor. figure 4. 4-phase parallel configurations 46501 f04 60.4k track1 track2 v out1 v outs1 v fb1 v fb2 comp1 4 paralleled outputs for 1.2v at 100a optional connection comp2 v outs2 v out2 60.4k 60.4k track1 track2 0.1f v out1 v outs1 v fb1 v fb2 comp1 comp2 v outs2 v out2 60.4k LTM4650-1 LTM4650-1 c th r fb 60.4k optional r fb 60.4k use to lower total equivalent resistance to lower i fb voltage error r th in parallel operation, the v fb pins have an i fb current of 20na maximum each channel. to reduce output voltage error due to this current , an additional v outs pin can be tied to v out , and an additional r fb resistor can be used to lower the total thevenin equivalent resistance seen by this current . for example in figure 4, the total thevenin equivalent resistance of the v fb pin is (60.4k//r fb ), which is 30.2k where r fb is ltm 4650-1 46501fc 13 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion output capacitors the LTM4650-1 is designed for low output voltage ripple noise and good transient response. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output volt - age ripple and transient requirements. c out can be a low esr tantalum capacitor, the low esr polymer capacitor or ceramic capacitor. the typical output capacitance range for each output is from 400f to 600f. additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 12.5a (25%) and 25a (50%) load step transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance . stability criteria are considered in the table 4 matrix, and the linear technology ltpower - cad design tool will be provided for stability analysis . in multi LTM4650-1 paralleling applications, table 4 rc compensation value is still valid in terms of having one set of rc filters on each of the paralleling modules while connecting all the comp, fb and v out pins together. see figure 29 and multiphase operation section. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancellation , but the output capacitance should be considered carefully as a function of stability and transient response. the linear technology ltpowercad design tool can calculate the output ripple reduction as the number of implemented phases increases by n times . a small value 10? to 50? resistor can be place in series from v out to the v outs pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. the same resistor could be place in series from v out to diffp and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. burst mode operation the LTM4650-1 is capable of burst mode operation on each regulator in which the power mosfets operate in - termittently based on load demand, thus saving quiescent current . for applications where maximizing the efficiency at very light loads is a high priority , burst mode operation should be applied . burst mode operation is enabled with the mode_pllin pin floating. during this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera - tion even though the voltage at the comp pin indicates a lower value . the voltage at the comp pin drops when the inductors average current is greater than the load requirement. as the comp voltage drops below 0.5v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450a for each output. the load current is now being supplied from the output capacitors. when the output voltage drops, caus - ing comp to rise above 0.5v, the internal sleep line goes low , and the LTM4650-1 resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats . either regulator can be configured for burst mode operation. pulse-skipping mode operation in applications where low output ripple and high effi - ciency at intermediate currents are desired, pulse-skipping mode should be used . pulse-skipping operation allows the LTM4650-1 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. tying the mode_pllin pin to intv cc enables pulse-skipping operation. at light loads the internal current comparator may remain tripped for several cycles and force the top mosfet to stay off for several cycles, thus skipping cycles. the inductor current does not reverse in this mode. this mode will maintain higher effective frequencies thus lower output ripple and lower noise than burst mode operation. either regulator can be configured for pulse-skipping mode. ltm 4650-1 46501fc 14 for more information www.linear.com/LTM4650-1 figure 5. examples of 2-phase, 4-phase, and 6-phase operation with phasmd table 46501 f05 v out2 180 phase 0 phase mode_pllin v out1 phasmd clkout 2-phase design 4-phase design 6-phase design 90 degree float v out2 180 phase 0 phase float mode_pllin v out1 phasmd clkout v out2 270 phase 90 phase float mode_pllin v out1 phasmd clkout 60 degree 60 degree v out2 180 phase 0 phase sgnd mode_pllin v out1 phasmd clkout v out2 240 phase 60 phase sgnd mode_pllin v out1 phasmd clkout v out2 300 phase 120 phase float mode_pllin v out1 phasmd clkout phasmd sgnd controller1 controller2 clkout float intv cc 0 0 0 180 180 240 60 90 120 forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode_pllin pin to gnd. in this mode, induc - tor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continu - ous mode is disabled and inductor current is prevented from reversing until the LTM4650-1 s output voltage is in regulation. either regulator can be configured for force continuous mode. multiphase operation for output loads that demand more than 25a of current, two outputs in LTM4650 -1 or even multiple LTM4650 -1 s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. the mode_pllin pin allows the LTM4650-1 to synchronize to an external clock (between 400khz and 780khz) and the internal phase-locked-loop allows the LTM4650-1 to lock onto incoming clock phase as well. the clkout signal can be connected to the mode_pllin pin of the following stage to line up both the frequency and the phase of the entire system. tying the phasmd pin to intv cc , sgnd, or floating generates a phase difference ( between mode_pllin and clkout) of 120 degrees , 60 degrees , or 90 degrees respectively. a total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the phasmd pin of each LTM4650-1 channel to different levels . figure 5 shows a 2-phase design, 4 -phase design and a 6-phase design example for clock phasing with the phasmd table. a pplica t ions i n f or m a t ion ltm 4650-1 46501fc 15 for more information www.linear.com/LTM4650-1 a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca - pacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by , the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. in multi LTM4650-1 s parallel applications, c th and r th values in table 4 are still valid to achieve a 3% transient response in a 25% load step. connect one set of rc (r th and c th ) network to the comp pin of each paralleling module like a dual phase single output setup. then connect the comp pins, fb pins, track/ss pin and v out pins from different modules together. see figure 29 for an example of parallel operation. ltpowercad power design tool can also be used to optimize loop compensation and transient performance if only one set of rc (r th and c th ) network is to be added to the common comp pins. the LTM4650-1 device is an inherently current mode controlled device , so parallel modules will have very good current sharing . this will balance the thermals on the design. figure 29 shows an example of parallel operation and pin connection. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current cancel - lation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases . figure 6 shows this graph. a pplica t ions i n f or m a t ion frequency selection and phase-lock loop (mode_pllin and f set pins) the LTM4650-1 device is operated over a range of fre - quencies to improve power conversion efficiency. it is recommended to operate the module at 400 khz for output voltage below 1.0v, 500khz for output voltage between 1.0v to 1.5v and 600khz for output voltage above 1.5v, for the best efficiency and inductor current ripple. the LTM4650-1 switching frequency can be set with an external resistor from the f set pin to sgnd. an accurate 10 a current source into the resistor will set a voltage that programs the frequency or a dc voltage can be applied. figure 7 shows a graph of frequency setting verses programming voltage. an external clock can be applied to the mode_pllin pin from 0 v to intv cc over a frequency range of 400khz to 780khz. the clock input high threshold is 1.6v and the clock input low threshold is 1v. the LTM4650-1 has the pll loop filter components on board. the frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock. both regulators will operate in continuous mode while being externally clock. the output of the pll phase detector has a pair of comple - mentary current sources that charge and discharge the internal filter network . when the external clock is applied then the f set frequency resistor is disconnected with an internal switch , and the current sources control the frequency adjustment to lock to the incoming external clock. when no external clock is applied, then the internal switch is on, thus connecting the external f set frequency set resistor for free run operation. ltm 4650-1 46501fc 16 for more information www.linear.com/LTM4650-1 figure 6. input rms current ratios to dc load current as a function of duty cycle duty factor (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 46501 f06 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase a pplica t ions i n f or m a t ion figure 7. operating frequency vs f set pin voltage f set pin voltage (v) 0 frequency (khz) 900 800 600 400 100 200 700 500 300 0 2 46501 f07 2.5 1 1.5 0.5 ltm 4650-1 46501fc 17 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion figure 8. example of output tracking application circuit minimum on-time minimum on-time t on is the smallest time duration that the LTM4650-1 is capable of turning on the top mosfet on either channel . it is determined by internal timing delays, and the gate charge required turning on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: v out v in ? freq > t on(min) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the output ripple and current will increase. the on-time can be increased by lowering the switching frequency. a good rule of thumb is to keep on-time longer than 110ns. output voltage tracking output voltage tracking can be programmed externally using the track pins. the output can be tracked up and down with another regulator. the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider to implement coincident tracking. the LTM4650-1 uses an accurate 60.4k resistor internally for the top feedback resistor for each channel. figure 8 shows an example of coincident tracking. equations: slave = 1 + 60.4k r ta ? ? ? ? ? ? ? v track v track is the track ramp applied to the slaves track pin. v track has a control range of 0v to 0.6v, or the internal reference voltage. when the masters output is divided down with the same resistor values used to set the slave s 46501 f08 LTM4650-1 v in temp run1 run2 track1 track2 f set c8 470f 6.3v r fb 60.4k r2 10k c6 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 pgood intv cc sgnd gnd 1.5v master ramp time t softstart = (c ss /1.3a) ? 0.6 diffp diffn diffout 40.2k 4.02k 2200pf pgood slave v out1 (master) 1.5v at 25a c7 470f 6.3v c5 100f 6.3v 4.02k 2200pf r4 121k r tb 60.4k 4v to 15v intermediate bus r6 100k c ss 0.1f c1 22f 25v r ta 60.4k c2 22f 25v c3 22f 25v c4 22f 25v c10 4.7f r9 10k intv cc v out2 (slave) 1.2v at 25a ltm 4650-1 46501fc 18 for more information www.linear.com/LTM4650-1 figure 9. output coincident tracking waveform time master output slave output output voltage 46501 f09 a pplica t ions i n f or m a t ion output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slave s regulation point. voltage tracking is disabled when v track is more than 0.6v. r ta in figure 8 will be equal to the r fb for coincident tracking . figure 9 shows the coincident tracking waveforms. as soon as v fb is below 0.54v regardless of the setting on the mode_pllin pin. ratiometric tracking can be achieved by a few simple cal - culations and the slew rate value applied to the masters track pin. as mentioned above, the track pin has a control range from 0 to 0.6v. the masters track pin slew rate is directly equal to the masters output slew rate in volts/time. the equation: mr sr ? 60.4k = r tb where mr is the master s output slew rate and sr is the slave s output slew rate in volts /time. when coincident tracking is desired, then mr and sr are equal, thus r tb is equal the 60.4k. r ta is derived from equation: r ta = 0.6v v fb 60.4k + v fb r fb ? v track r tb where v fb is the feedback voltage reference of the regula - tor, and v track is 0.6v. since r tb is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r ta is equal to r fb with v fb = v track . therefore r tb = 60.4k, and r ta = 60.4 k in figure 8. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r tb can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. for example, mr = 1.5v/1ms, and sr = 1.2v/1ms. then r tb = 76.8k. solve for r ta to equal to 49.9k. each of the track pins will have the 1.3 a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an offset on the track pin input . smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4 k is used then a 6.04k can be used to reduce the track pin offset to a negligible value. the track pin of the master can be controlled by a capacitor placed on the master regulator track pin to ground. a 1.3 a current source will charge the track pin up to the reference voltage and then proceed up to intv cc . after the 0.6v ramp, the track pin will no longer be in control, and the internal voltage reference will control output regulation from the feedback divider. foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. the track pins are pulled low when the run pin is below 1.2v. the total soft-start time can be calculated as: t soft-start = c ss 1.3a ? ? ? ? ? ? ? 0.6 regardless of the mode selected by the mode_pllin pin, the regulator channels will always start in pulse-skipping mode up to track = 0.5v. between track = 0.5v and 0.54v, it will operate in forced continuous mode and revert to the selected mode once track > 0.54v. in order to track with another channel once in steady state operation , the LTM4650-1 is forced into continuous mode operation ltm 4650-1 46501fc 19 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion power good the pgood pins are open drain pins that can be used to monitor valid output voltage regulation. this pin monitors a 10% window around the regulation point. a resistor can be pulled up to a particular supply voltage no greater than 6v maximum for monitoring. stability compensation the LTM4650-1 has a built-in 10pf high frequency filter capacitor from comp to sgnd on each output channel. an external rc filtering circuit is required to add from comp to sgnd to achieve fast type ii control loop compensation . table 4 is provided for most application requirements. the linear technology module power design tool (ltpower - cad) will be provided for other control loop optimization. run enable the run pins have an enable threshold of 1.4 v maximum, typically 1.25 v with 150mv of hysteresis. they control the turn on each of the channels and intv cc . these pins can be pulled up to v in for 5 v operation, or a 5 v zener diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5v input for enabling the channels. the run pins can also be used for output voltage sequencing. in parallel operation the run pins can be tie together and controlled from a single control . see the typical applica - tion circuits in figure 24. int v cc and extv cc the LTM4650-1 module has an internal 5v low dropout regulator that is derived from the input voltage. this regu - lator is used to power the control circuitry and the power mosfet drivers . this regulator can source up to 70ma, and typically uses ~30ma for powering the device at the maximum frequency. this internal 5v supply is enabled by either run1 or run2. extv cc allows an external 5 v supply to power the LTM4650 -1 and reduce power dissipation from the internal low dropout 5v regulator. the power loss savings can be calculated by: ( v in C 5v) ? 30ma = ploss extv cc has a threshold of 4.7v for activation, and a maximum rating of 6v. when using a 5 v input, connect this 5 v input to extv cc also to maintain a 5v gate drive level. extv cc must sequence on after v in , and extv cc must sequence off before v in . differential remote sense amplifier an accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. this is especially true for high current loads. the amplifier can be used on one of the two channels, or on a single parallel output. it is very important that the diffp and diffn are connected properly at the output, and diffout is connected to either v outs1 or v outs2 . in parallel operation, the diffp and diffn are connected properly at the output, and diffout is connected to one of the v outs pins. review the parallel schematics in figure 25 and review figure 4. sw pins the sw pins are generally for testing purposes by moni - toring these pins . these pins can also be used to dampen out switch node ringing caused by lc parasitic in the switched current paths . usually a series r-c combina - tion is used called a snubber circuit . the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor . if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the power path board inductance in combination with the mosfet interconnect bond wire inductance. first the sw pin can be monitored with a wide bandwidth scope with a high frequency scope probe. the ring fre - quency can be measured for its value. the impedance z can be calculated : zl = 2fl, where f is the resonant frequency of the ring , and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that ltm 4650-1 46501fc 20 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion and by definition must always be less than i d . combining all of the constants into one term: k d = ? k q where k d = 8.62 ? 10 ?5 , and knowing ln(i d /i s ) is always positive because i d is always greater than i s , leaves us with the equation that: v d = t kelvin ( ) ? k d ? in i d i s where v d appears to increase with temperature. it is com - mon knowledge that a silicon diode biased with a current sour ce has an approximate C2mv/c temperature relation - ship ( figure 10), which is at odds with the equation. in fact, the i s term increases with temperature, reducing the ln(i d /i s ) absolute value yielding an approximate C2mv/c composite diode voltage slope. its impedance is equal to the resistor at the ring frequency . calculated by: zc = 1/(2 fc). these values are a good place to start with. modification to these components should be made to attenuate the ringing with the least amount of power loss. temperature monitoring measuring the absolute temperature of a diode is pos - sible due to the relationship between current, voltage and temperature described by the classic diode equation : i d = i s ? e v d ? v t ? ? ? ? ? ? or v d = ? v t ? in i d i s where i d is the diode current , v d is the diode voltage , is the ideality factor (typically close to 1.0) and i s (satura- tion current) is a process dependent parameter. v t can be broken out to: v t = k ? t q where t is the diode junction temperature in kelvin , q is the electron charge and k is boltzmanns constant. v t is approximately 26 mv at room temperature (298k) and scales linearly with kelvin temperature. it is this linear temperature relationship that makes diodes suitable tem - perature sensors. the i s term in the previous equation is the extrapolated current through a diode junction when the diode has zero volts across the terminals. the i s term varies from process to process, varies with temperature, figure 10. diode voltage v d vs temperature t(c) temperature (c) ?50 ?25 0.3 diode voltage (v) 0.5 0.8 0 50 75 0.4 0.7 0.6 25 100 46501 f10 125 ltm 4650-1 46501fc 21 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion to obtain a linear voltage proportional to temperature we cancel the i s variable in the natural logarithm term to remove the i s dependency from the equation 1. this is accomplished by measuring the diode voltage at two cur - rents i 1 , and i 2 , where i 1 = 10 ? i 2 ) and subtracting we get: v d = t(kelvin) ? k d ? in i 1 i s C t(kelvin) ? k d ? in i 2 i s combining like terms, then simplifying the natural log terms yields: v d = t(kelvin) ? k d ? ln(10) and redefining constant k' d = k d ? in(10) = 198v k yields v d = k' d ? t(kelvin) solving for temperature: t(kelvin) = v d k' d ( celsius) = t(kelvin)C 273.15 where 300 k = 27c means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198v per kelvin of the junction with a zero intercept at 0 kelvin. the diode connected pnp transistor at the temp pin can be used to monitor the internal temperature of the LTM4650-1. see figure 25 for an example. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param - eters defined by jesd51-9 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a module package mounted to a hardware test board also defined by jesd 51-9 ( test boards for area array surface mount package thermal measurements). the motivation for providing these thermal coefficients is found in jesd 51-12 ( guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulator s thermal performance in their ap - plication at various electrical and environmental operating conditions to compliment any fea activities . without fea software, the thermal resistances reported in the pin con - figuration section are in-and-of themselves not relevant to providing guidance of thermal per formance ; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section typically gives four thermal coefficients explicitly defined in jesd 51-12; these coef - ficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board , which does not reflect an actual application or viable operating condition. 2. jcbottom , the thermal resistance from junction to the bottom of the product case , is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. in the typical module, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. ltm 4650-1 46501fc 22 for more information www.linear.com/LTM4650-1 figure 11. graphical representation of jesd51-12 thermal coefficients 46501 f11 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb , the thermal resistance from junction to the printed circuit board , is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a por - tion of the board. the board temperature is measured a specified distance from the package , using a two sided, two layer board. this board is described in jesd 51-9. a graphical representation of the aforementioned thermal resistances is given in figure 11; blue resistances are contained within the module regulator, whereas green resistances are external to the module. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal a pplica t ions i n f or m a t ion operating conditions of a module. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclu - sively through the top or exclusively through bottom of the module as the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the package granted, in the absence of a heat sink and airflow , a majority of the heat flow is into the board. within a sip (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicitybut also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet : (1) initially, fea software is used to accurately build the mechanical geometry of the module and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions ; (2) this model simulates a software-defined jedec environment consistent with jsed51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values ; (3) the model ltm 4650-1 46501fc 23 for more information www.linear.com/LTM4650-1 and fea software is used to evaluate the module with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. an outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. after these laboratory test have been performed and correlated to the module model, then the jb and ba are summed together to cor - relate quite well with the module model with no airflow or heat sinking in a properly define chamber . this jb + ba value is shown in the pin configuration section and should accurately equal the ja value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. the LTM4650-1 module has been designed to effectively remove heat from both the top and bottom of the pack - age. the bottom substrate material has very low thermal resistance to the printed cir cuit board . an external heat sink can be applied to the top of the device for excellent heat sinking with airflow. figure 12 shows a temperature plot of the LTM4650-1 with 12 v input , 1.0v output at 50a without heat sink and a no airflow condition. safety considerations the LTM4650-1 modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the device does support over current protection. a temperature diode is provided for monitoring internal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the run pin. a pplica t ions i n f or m a t ion figure 12. thermal image 12v to 1v, 50a with no air flow and no heat sink (based on 4-layer 101mm 114mm pcb board containing 2oz copper on the top , bottom and all internal layers) ltm 4650-1 46501fc 24 for more information www.linear.com/LTM4650-1 power derating the 0.9 v and 1.5 v power loss curves in figure 14 and figure 15 can be used in coordination with the load current derating curves in figure 16 to figure 23 for calculating an approximate ja thermal resistance for the LTM4650- 1 with various heat sinking and airflow conditions. the power loss curves are taken at room temperature , and are increased with a 1.2 multiplicative factor at 120c. the derating curves are plotted with ch 1 and ch2 in parallel single output operation starting at 50a of load with low ambient temperature. the output voltages are 0.9v and 1.5v. these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without airflow . the power loss increase with ambient temperature change is factored into the derating curves . the junctions are maintained at ~120c maximum while lowering output current or power while increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example in figure 17, the load current is derated to ~35a at ~90c with 200 lfm air but not heat sink and the power loss for the 12 v to 0.9v at 35a output is a ~5.6w loss. the 5.6w loss is calculated with the ~4.7w room temperature loss from the 12v to 0.9 v power loss curve at 35a, and the 1.20 multiplying factor at 120 c junction temperature. if the 90 c ambient temperature is subtracted from the 120c junction temperature, then the difference of 30c divided 5.5w equals a 5.4c/w ja thermal resistance. table 2 specifies a 5.5c/w value which is pretty close. tables 2 and 3 provide equivalent thermal resistances for 0.9 v and 1.5v outputs with and without airflow and heat sinking. the derived thermal resistances in tables 2 and 3 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the efficiency curves and adjusted with the above ambient temperature multiplicative factors. the printed circuit board is a 1.6mm thick 4 -layer board with 2 oz? copper on each layer. the pcb dimensions are 101mm 114mm. the bga heat sinks are listed in table 3. a pplica t ions i n f or m a t ion ltm 4650-1 46501fc 25 for more information www.linear.com/LTM4650-1 figure 13. recommended pcb layout gnd gnd gnd sgnd cntrl cntrl v out1 c out1 c out2 v out2 v in c in1 c in2 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a 46501 f13 layout checklist/example the high integration of LTM4650-1 makes the pcb board layout very simple and easy . however, to optimize its electrical and thermal performance , some layout consid - erations are still necessary. ? use large pcb copper areas for high current paths , including v in , gnd, v out1 and v out2 . it helps to mini - mize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the?unit. ? to minimize the via conduction loss and reduce module thermal stress , use multiple vias for interconnection between top layer and other power layers. a pplica t ions i n f or m a t ion ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules , tie the v out , v fb , and comp pins together. use an internal layer to closely connect these pins together. the track pin can be tied a common capacitor for regulator soft-start. ? bring out test points on the signal pins for monitoring. figure 13 gives a good example of the recommended layout. lga and bga pcb layouts are identical with the exception of circle pads for bga (see package description). ltm 4650-1 46501fc 26 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion table 2. 0.9v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 16, 17 5, 12 figure 14 0 none 7.5 figures 16, 17 5, 12 figure 14 200 none 5.5 figures 16, 17 5, 12 figure 14 400 none 5 figures 18, 19 5, 12 figure 14 0 bga heat sink 7 figures 18, 19 5, 12 figure 14 200 bga heat sink 4.5 figures 18, 19 5, 12 figure 14 400 bga heat sink 4 table 3. 1.5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 20, 21 5, 12 figure 15 0 none 7.5 figures 20, 21 5, 12 figure 15 200 none 5.5 figures 20, 21 5, 12 figure 15 400 none 5 figures 22, 23 5, 12 figure 15 0 bga heat sink 7 figures 22, 23 5, 12 figure 15 200 bga heat sink 4.5 figures 22, 23 5, 12 figure 15 400 bga heat sink 4 heat sink manufacturer part number website wakefield lt n 20069-t5 wakefield-vette.com table 4. output voltage response vs component matrix (refer to figure 23) load step typical measured values 2-phase single output solution c in (ceramic) c out (ceramic) c out (bulk) vendors value part number vendors value part number vendors value part number murata 22f, 16v, x5r, 1210 grm32er61c226ke20l murata 100f, 6.3v, x5r, 1210 grm32er60j107me20l panasonic 680f, 2.5v, 6m 2r5tpf680m6l murata 22f, 16v, x5r, 1206 grm31cr61c226ke15k murata 220f, 4v, x5r, 1206 grm31cr60g227m panasonic 470f 2.5v, 3m? eefgx 0e471r tdk 22f, 16v, x5r, 1210 c 3225 x5r1c 226m 250aa taiyo yuden 100f, 6.3v, x5r, 1210 jmk325bj107mm-t taiyo yuden 220f, 4v, x5r, 1210 amk325abj227mm-t ltm 4650-1 46501fc 27 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion 25% load step (0a to 12.5a) ceramic output capacitor only solutions peak-peak deviation percentage v in v out c in * (bulk) c in ( ceramic) c out (bulk) c out (ceramic) comp pin parallel capacitor (cthp) comp pin resistor (r th ) comp pin capacitor (c th ) feed- forward capacitor (c ff ) peak- peak deviation (v pk-pk ) settling time (t settle ) ctrl loop band- width (bw) ctrl loop phase margin (pm) load step (a) load step slew rate r fb (k) freq (khz) 3% (<60mv) 12v 1v 150f 22f x 2 none 220f x 6 33pf 3.24k 10nf 68pf 53mv 80s 88khz 47 deg 12.5 10a/s 90.9 500 3% (<72mv) 12v 1.2v 150f 22f x 2 none 220f x 5 33pf 3.24k 10nf 68pf 56mv 80s 89khz 49 deg 12.5 10a/s 60.4 500 3% (<90mv) 12v 1.5v 150f 22f x 2 none 220f x 4 33pf 3.24k 10nf 68pf 58mv 80s 91khz 58 deg 12.5 10a/s 40.2 600 3% (<108mv) 12v 1.8v 150f 22f x 2 none 220f x 4 33pf 3.24k 10nf 68pf 64mv 90s 98khz 65 deg 12.5 10a/s 30.2 600 25% load step (0a to 9a) bulk + ceramic output capacitor solutions peak-peak deviation percentage v in v out c in * (bulk) c in ( ceramic) c out (bulk) c out (ceramic) comp pin parallel capacitor (cthp) comp pin resistor (r th ) comp pin capacitor (c th ) feed- forward capacitor (c ff ) peak- peak deviation (v pk-pk ) settling time (t settle ) ctrl loop band- width (bw) ctrl loop phase margin (pm) load step (a) load step slew rate r fb (k) freq (khz) 3% (<60mv) 12 v 1v 150f 22f 2 470f 2 100f 4 33pf 3.16k 3300pf 68pf 55mv 30s 82khz 68 deg 12.5 10a/s 90.9 500 3% (<72mv) 12v 1.2v 150f 22f 2 470f 2 100f 4 33pf 3.16k 3300pf 68pf 55mv 30s 82khz 73 deg 12.5 10a/s 60.4 500 3% (<90mv) 12v 1.5v 150f 22f 2 470f 2 100f 4 82pf 4.12k 3300pf none 64mv 30s 59khz 53 deg 12.5 10a/s 40.2 600 3% (<108mv) 12v 1.8v 150f 22f 2 470f 2 100f 4 82pf 4.12k 3300pf none 75mv 30s 51khz 58 deg 12.5 10a/s 30.2 600 50% load step (0a to 25a) ceramic output capacitor only solutions peak-peak deviation percentage v in v out c in * (bulk) c in ( ceramic) c out (bulk) c out (ceramic) comp pin parallel capacitor (cthp) comp pin resistor (r th ) comp pin capacitor (c th ) feed- forward capacitor (c ff ) peak- peak deviation (v pk-pk ) settling time (t settle ) ctrl loop band- width (bw) ctrl loop phase margin (pm) load step (a) load step slew rate r fb (k) freq (khz) 3% (<60mv) 12v 1v 150f 22f 2 none 220f 12 33pf 6.81k 4.7nf 100pf 58mv 80s 76khz 45 deg 25 10a/s 90.9 500 3% (<72mv) 12v 1.2v 150f 22f 2 none 220f 12 33pf 6.81k 4.7nf 100pf 61mv 80s 77khz 50 deg 25 10a/s 60.4 500 3% (<90mv) 12v 1.5v 150f 22f 2 none 220f 14 33pf 5.90k 4.7nf none 90mv 80s 47khz 45 deg 25 10a/s 40.2 600 3% (<108mv) 12v 1.8v 150f 22f 2 none 220f 14 33pf 5.90k 4.7nf none 105mv 90s 43khz 50 deg 25 10a/s 30.2 600 50% load step (0a to 25a) bulk + ceramic output capacitor solutions peak-peak deviation percentage v in v out c in * (bulk) c in ( ceramic) c out (bulk) c out (ceramic) comp pin parallel capacitor (cthp) comp pin resistor (r th ) comp pin capacitor (c th ) feed- forward capacitor (c ff ) peak- peak deviation (v pk-pk ) settling time (t settle ) ctrl loop band- width (bw) ctrl loop phase margin (pm) load step (a) load step slew ra te r fb (k) freq (khz) 3% (<60mv) 12v 1v 150f 22f 2 470f 6 100f 4 33pf 12.0k 3300pf 47pf 47mv 30s 70khz 57 deg 25 10a/s 90.9 500 3% (<72mv) 12v 1.2v 150f 22f 2 470f 6 100f 4 33pf 12.0k 3300pf 47pf 48mv 30s 67khz 65 deg 25 10a/s 60.4 500 3% (<90mv) 12v 1.5v 150f 22f 2 470f 6 100f 4 68pf 10.2k 3300pf none 56mv 40s 50khz 49 deg 25 10a/s 40.2 600 3% (<108mv) 12v 1.8v 150f 22f 2 470f 6 100f 4 82pf 14.5k 3300pf none 58mv 50s 51khz 46 deg 25 10a/s 30.2 600 *bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads. ltm 4650-1 46501fc 28 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion figure 14. 0.9v output power loss curve figure 15. 1.5v output power loss curve figure 16. 5v to 0.9v derating curve, no heat sink load current (a) 0 0 powe loss (w) 4 3 2 1 5 9 8 7 6 10 40 50 10 20 46501 f14 30 v in = 5v v in = 12v load current (a) 0 0 powe loss (w) 4 3 2 1 5 9 8 7 6 10 40 50 10 20 46501 f15 30 v in = 5v v in = 12v ambient temperature (c) 25 output current (a) 20 30 40 105 46501 f16 10 0 45 65 85 35 115 55 75 95 60 50 0lfm 200lfm 400lfm figure 17. 12v to 0.9v derating curve, no heat sink figure 18. 5v to 0.9v derating curve, bga heat sink figure 19. 12v to 0.9v derating curve, bga heat sink ambient temperature (c) 25 output current (a) 20 30 40 105 46501 f17 10 0 45 65 85 35 115 55 75 95 60 50 0lfm 200lfm 400lfm ambient temperature (c) 25 output current (a) 20 30 40 105 46501 f18 10 0 45 65 85 35 115 55 75 95 60 50 0lfm 200lfm 400lfm ambient temperature (c) 25 output current (a) 20 30 40 105 46501 f19 10 0 45 65 85 35 115 55 75 95 60 50 0lfm 200lfm 400lfm figure 20. 5v to 1.5v derating curve, no heat sink figure 21. 12v to 1.5v derating curve, no heat sink ambient temperature (c) 25 output current (a) 20 30 40 105 46501 f20 10 0 45 65 85 35 115 55 75 95 60 50 0lfm 200lfm 400lfm ambient temperature (c) 25 output current (a) 20 30 40 105 46501 f21 10 0 45 65 85 35 115 55 75 95 60 50 0lfm 200lfm 400lfm ltm 4650-1 46501fc 29 for more information www.linear.com/LTM4650-1 a pplica t ions i n f or m a t ion figure 22. 5v to 1.5v derating curve, bga heat sink figure 23. 12v to 1.5v derating curve, bga heat sink ambient temperature (c) 25 output current (a) 20 30 40 105 46501 f22 10 0 45 65 85 35 115 55 75 95 60 50 0lfm 200lfm 400lfm ambient temperature (c) 25 output current (a) 20 30 40 105 46501 f23 10 0 45 65 85 35 115 55 75 95 60 50 0lfm 200lfm 400lfm figure 24. typical 4.5v in to 15v in , 1.5v and 1.2v at 25a outputs 46501 f24 LTM4650-1 v in temp run1 run2 track1 track2 f set r fb2 60.4k r2 10k phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 pgood1 intv cc sgnd gnd track1 track2 diffn diffp diffout r fb1 40.2k pgood2 v out2 1.2v at 25a c out3 100f 6.3v c out4 470f 6.3v r4 121k r7 100k c5 0.1f c9 0.1f c1 22f 25v 4 c10 4.7f v out1 1.5v at 25a r3 10k intv cc + c in (opt) v in 4.5v to 15v intv cc + c out1 100f 6.3v c out2 470f 6.3v + 6.49k 4700pf 6.49k 4700pf ltm 4650-1 46501fc 30 for more information www.linear.com/LTM4650-1 typical a pplica t ions figure 25. LTM4650-1 2-phase, 1v at 50a design figure 26. 25%, 12.5a load step transient waveform of figure 23 circuit figure 27. bode plot of figure 23 circuit 46501 f25 LTM4650-1 v in temp run1 run2 run monitor temp track1 track track2 f set r5 90.9k c out1 220f 4v 6 phasmd v out1 v out2 v outs1 sw1 v fb1 v fb2 comp1 comp2 v out2 v outs2 sw2 pgood2 pgood mode_pllin clkout intv cc extv cc pgood1 pgood r2 10k intv cc sgnd gnd diffn diffp diffout r4 121k c9 0.1f c in 22f 25v 4 c10 4.7f intv cc v in 4.5v to 15v v out 1v 50a *see table 4 68pf 3.24k 10nf 33pf 50s/div v out(ac) 20mv/div load step 10a/div 46501 f26 54mv phase gain (db) 46501 f27 ltm 4650-1 46501fc 31 for more information www.linear.com/LTM4650-1 t ypical a pplica t ions figure 28. LTM4650-1 1.2v and 1v output tracking 46501 f28 LTM4650-1 v in temp run1 run2 track1 track2 f set c out2 470f 6.3v r8 90.9k r2 10k c out1 100f 6.3v 2 phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 pgood1 intv cc intv cc sgnd gnd v out1 1.2v diffp diffn diffout r5 60.4k pgood2 v out2 1v at 25a c out2 470f 6.3v c out1 100f 6.3v 2 r9 60.4k r6 100k c5 0.1f r7 90.9k c in 22f 25v 4 c10 4.7f + + r3 10k v out1 1.2v 25a v in 4.5v to 15v intv cc r4 121k 6.34k 1500pf 6.34k 1500pf ltm 4650-1 46501fc 32 for more information www.linear.com/LTM4650-1 t ypical applica t ions figure 29. LTM4650-1 4-phase, 1.2v at 100a 46501 f29 LTM4650-1 v in temp run1 run2 track1 track track2 f set c out2 470f 6.3v r5 60.4k r2 5k c out1 100f 6.3v 2 phasmd v out1 v outs1 sw1 v fb1 v fb2 v out2 v outs2 sw2 pgood2 pgood mode_pllin clkout clk1 clk1 intv cc extv cc pgood1 pgood sgnd gnd diffp diffn diffout c out2 470f 6.3v c out1 100f 6.3v 2 r4 121k r6 100k c in1 22f 25v 3 c10 4.7f + + LTM4650-1 v in c out2 470f 6.3v c out1 100f 6.3v 2 v in 4.5v to 15v v out1 v outs1 sw1 v fb1 v fb2 v fb v outs2 v out2 sw2 pgood2 pgood mode_pllin clkout intv cc extv cc pgood1 pgood sgnd gnd diffp diffn diffout c out2 470f 6.3v c out1 100f 6.3v 2 r9 100k c19 0.22f c in2 22f 25v 3 c16 4.7f + + intv cc track v fb 68pf intv cc v out 1.2v 100a intv cc run run 3.16k 3300pf comp1 comp2 r10 121k 3.16k 3300pf temp run1 run2 track1 track2 f set phasmd comp1 comp2 33pf 33pf comp ltm 4650-1 46501fc 33 for more information www.linear.com/LTM4650-1 LTM4650-1 component bga pinout p ackage descrip t ion pin id function pin id function pin id function pin id function pin id function pin id function a1 v out1 b1 v out1 c1 v out1 d1 gnd e1 gnd f1 gnd a2 v out1 b2 v out1 c2 v out1 d2 gnd e2 gnd f2 gnd a3 v out1 b3 v out1 c3 v out1 d3 gnd e3 gnd f3 gnd a4 v out1 b4 v out1 c4 v out1 d4 gnd e4 gnd f4 mode_pllin a5 v out1 b5 v out1 c5 v out1s d5 v fb1 e5 track1 f5 run1 a6 gnd b6 gnd c6 f set d6 sgnd e6 comp1 f6 sgnd a7 gnd b7 gnd c7 sgnd d7 v fb2 e7 comp2 f7 sgnd a8 v out2 b8 v out2 c8 v out2s d8 track2 e8 diffp f8 diffout a9 v out2 b9 v out2 c9 v out2 d9 gnd e9 diffn f9 run2 a10 v out2 b10 v out2 c10 v out2 d10 gnd e10 gnd f10 gnd a11 v out2 b11 v out2 c11 v out2 d11 gnd e11 gnd f11 gnd a12 v out2 b12 v out2 c12 v out2 d12 gnd e12 gnd f12 gnd pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 gnd j1 gnd k1 gnd l1 gnd m1 gnd g2 sw1 h2 gnd j2 v in k2 v in l2 v in m2 v in g3 gnd h3 gnd j3 v in k3 v in l3 v in m3 v in g4 phasemd h4 gnd j4 v in k4 v in l4 v in m4 v in g5 clkout h5 gnd j5 gnd k5 gnd l5 v in m5 v in g6 sgnd h6 gnd j6 temp k6 gnd l6 v in m6 v in g7 sgnd h7 gnd j7 extv cc k7 gnd l7 v in m7 v in g8 pgood2 h8 intv cc j8 gnd k8 gnd l8 v in m8 v in g9 pgood1 h9 gnd j9 v in k9 v in l9 v in m9 v in g10 gnd h10 gnd j10 v in k10 v in l10 v in m10 v in g11 sw2 h11 gnd j11 v in k11 v in l11 v in m11 v in g12 gnd h12 gnd j12 gnd k12 gnd l12 gnd m12 gnd ltm 4650-1 46501fc 34 for more information www.linear.com/LTM4650-1 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . p ackage descrip t ion please refer to http://www .linear.com/product/LTM4650-1#packaging for the most recent package drawings. bga package 144-lead (16mm 16mm 5.01mm) (reference ltc dwg # 05-08-1523 rev ?) package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes d e b e e b f g bga 144 1215 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module detail a pin 1 l k j h g f e d c b m a 1 2 3 4 5 6 7 8 10 9 11 12 suggested pcb layout top view 0.0000 0.0000 0.630 0.025 ? 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 detail a ?b (144 places) a detail b package side view z m x yzddd m zeee a2 detail b substrate a1 b1 ccc z mold cap symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 144 // bbb z z h2 h1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes ltm 4650-1 46501fc 35 for more information www.linear.com/LTM4650-1 r evision h is t ory rev date description page number a 05/16 added snpb ball finish 1, 2 b 07/16 added LTM4650-1a connected comp pin of master and slave devices 1, 2, 3, 4, 10 30 c 12/16 corrected part marking and finished code 2 ltm 4650-1 46501fc 36 for more information www.linear.com/LTM4650-1 ? linear technology corporation 2016 lt 1216 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTM4650-1 r ela t e d p ar t s p ackage p ho t o design r esources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation t ools manufacturing: ? quick start guide ? pcb design , assembly and manufacturing guidelines ? package and board level reliability module regulator products sear ch 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power sear ch parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. bga part number description comments LTM4650 LTM4650-1 with internal compensation 4.5v v in 15v, dual 25a or single 50a ltm4630 lower current than LTM4650; dual 18a or single 36a pin compatible with LTM4650; 4.5v v in 15v, 0.6v v out 1.8v, 15mm 15mm 4.41mm lga and 15mm 15mm 5.01mm bga packages ltm 4630a lower current and higher v out than LTM4650; up to 5.3v out , dual 18a or single 26a pin compatible with LTM4650; 4.5v v in 15v, 0.6v v out 5.3v, 15mm 15mm 4.41mm lga package ltm 4630-1 lower current than LTM4650 with external compensation and 0.8% (C1a) or 1.5% (C1b) v out accuracy pin compatible with LTM4650; 4.5v v in 15v, 0.6v v out 1.8v, 15mm 15mm 5.01mm bga package ltm 4620 lower current than LTM4650; dual 13a or single 26a. pin compatible with LTM4650; 4.5v v in 16v, 0.6v v out 2.5v, 15mm 15mm 4.41mm lga and 15mm 15mm 5.01mm bga packages ltm 4620a lower current and higher v out than LTM4650; up to 5.3v out , dual 13a or single 26a. pin compatible with LTM4650; 4.5v v in 16v, 0.6v v out 2.5v, 15mm 15mm 4.41mm lga and 15mm 15mm 5.01mm bga packages ltm 4628 lower current, higher v in and v out than LTM4650; dual 8a or single 16a pin compatible with LTM4650; 4.5v v in 26.5v, 0.6v v out 5.5v, 15mm 15mm 4.32mm lga and 15mm 15mm 4.92mm bga packages ltm 4677 dual 18a or single 36a with psm 4.5v v in 16 v, 0.5v v out 1.8 v. 16mm 16mm 5.01mm bga package ltm4639 lower v in (2.375v v in 7v), 20a 0.6v v out 5.5v. 15mm 15mm 4.92mm bga package ltm 4650-1 46501fc |
Price & Availability of LTM4650
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |